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www.fairchildsemi.com ? 2009 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.2 ? 5/21/10 an-6300 fan6300 / fan6300a / FAN6300H highly integrated quasi-resonant pwm controller abstract this application note describes a detailed design strategy for higher-power conversion efficiency and better emi using a quasi-resonant pwm cont roller compared to the conventional, hard-switched converter with a fixed switching frequency. based on the proposed design guideline, a design example with detailed parameters demonstrates the performance of the controller. introduction the highly integrated fan6300/a/h pwm controller provides several features to enhance the performance of flyback converters. fan6300/a are applied on quasi- resonant flyback converter where maximum operating frequency is below 100khz and FAN6300H is suitable for high frequency operation that is around 190khz. a built-in high voltage (hv) startup circuit can provide more startup current to reduce the startup time of the controller. once the vdd voltage exceeds the turn-on threshold voltage, the hv startup function is disabled immediately to reduce power consumption. an internal valley voltage detector ensures power system operates in quasi-resonant operation in wide- range line voltage and reduces switching loss to minimize switching voltage on drain of the power mosfet. to minimize standby power consumption and improve light- load efficiency, a proprietary green-mode function provides off-time modulation to decrease switching frequency and perform extended valley voltage switching to keep to a minimum switching voltage. fan6300/a/h controller provides many protection functions. pulse-by-pulse current limiting ensures the fixed peak current limit level, even when short-circuit occurs. once an open-circuit failure occurs in the feedback loop, the internal protection circuit disables pwm output immediately. as long as v dd drops below the turn-off threshold voltage, the controller also disables the pwm output. the gate output is clamped at 18v to protect the power mos from high gate-source voltage conditions. the minimum t off time limit prevents the system frequency from being too high. if the det pin reaches ovp level, internal otp is triggered, and the power system enters latch-mode until ac power is removed.
an-6300 application note ? 2009 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.2 ? 5/21/10 2 figure 1. basic quasi-resonant converter cs 8 6 2 3 1 4 7 5 0.3v drv gnd vdd two steps uvlo 16v/10v/8v internal bias latched 18v gate det fb nc hv latched 4.2v 2r r soft-start 5ms pwm current limit i det internal otp latched s/h blanking circuit t off-min (8s/38s) i det 5v det ovp 2.5v t off blanking (4s) q q set clr s r fb olp timer 55ms over-power compensation v det starter 30s latched valley detector 0.3v 27v ovp v det i hv 1st valley t off-min +9s 2ms (3s/13s) for h version t off-min +5s for h version (1.5s) for h version figure 2. functional block diagram
an-6300 application note ? 2009 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.2 ? 5/21/10 3 design procedure for the primary-side inductance of transformer in this section, a design procedure is described using the schematic of figure 1 as a reference. [a] define the system specifications ? line voltage range ( v in,min and v in,max ) ? maximum output power ( p o ). ? output voltage ( v o ) and maximum output current ( i o ) ? estimated efficiency ( ) the power conversion efficiency must be estimated to calculate the maximum input power. in the case of nb adaptor applications, the typi cal efficiency is 85%~90%. with the estimated efficiency, the maximum input power is given by: o in p p= (1) [b] estimate reflected output voltage figure 3 shows the typical waveforms of the drain voltage of quasi-resonant flyback converter. when the mosfet is turned off, the dc link voltage ( v o ), together with the output voltage ( v o ) and the forward voltage drop of the schottky diode ( v d ) reflected to the primary, are imposed on the mosfet. the maximum nominal voltage across the mosfet ( v ds ) is: ds,max in,max o d vv+nv+v =() (2) where the turns ratio of primary to secondary side of transformer is defined as n and v ds is as specified in equation 2. by increasing n , the capacitive switching loss and conduction loss of the mosfet is reduced. however, this increases the voltage stress on the mosfet as shown in figure 3. therefore, determine n by a trade-off between the voltage margin of the mosfet and the efficiency. typically, a turn-off voltage spike of v ds is considered as 100v, thus v ds,max is designed around 490~550v (75~85% of mosfet rated voltage). [c] determine the transformer primary-side inductance ( l p ) figure 4 shows the typical waveforms of mosfet drain current ( i ds ), secondary diode current ( i d ), and the mosfet drain voltage ( v ds ) of a qr converter. during t off , the current flows through the secondary side rectifier diode. when i d reduces to zero, v ds begins to drop by the resonance between the effective output capacitor of the mosfet and the primary-side inductance ( l p ). to minimize the switching loss, the fan6300/a/h is designed to turn on the mosfet when v ds reaches its minimum voltage v in -n(v o +v d ) . v in + - v o + - c oss v ds + - + - v ds v in,max n(v o +v d ) v ds 0v n(v o +v d ) n(v o +v d ) n(v o +v d ) +- v d n(v o +v d ) n:1 figure 3. typical waveform of mosfet drain voltage for qr operation i ds i d v ds v in v in +n(v o +v d ) t on t off t f t s n(v o +v d ) v in -n(v o +v d ) n(v o +v d ) i in i ds pk dt s figure 4. typical waveform of qr operation
an-6300 application note ? 2009 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.2 ? 5/21/10 4 to determine the primary-side inductance ( l p ), the following variables should be determined beforehand: ? the minimum switching frequency ( f s,min ) : the maximum average input current occurs at the minimum input voltage and full-load condition. meanwhile, the switching frequency is at minimum value during qr operation. ? the falling time of the mosfet drain voltage (t f ): as shown in figure 4, the falling time of mosfet drain voltage is half of the resonant period of the mosfet effective output capacitance and primary- side inductance. if a resonant capacitor is added to be paralleled with c oss , t f can be increased and emi can be reduced. however, this forces a switching loss increase. the typical value of t f for nb adaptor application is about 0.5~1 s. after determining f s,min and t f , the maximum duty cycle is calculated as: od max s,min f od in nv+v d(1-ft) n v +v +v () = () (3) where v in,min is specified at low-line and full-load. according to equation 1, the maximum average input current i in,max is determined as oo in,max in,min vi i v = (4) according to figure 3, i in,max can be obtained as: = p k in,max max ds,max 1 idi 2 (5) i ds,max pk can be determined as: = pk in,min max ds,max ms,min vd i lf (6) in equation 5, replace i ds,max pk by equation 6, then combine equations 4 and 5 to obtain l p : 2 in,min max p in s,min (v d l 2p f ) = (7) where p in , and d max are specified in equations 1 and 3, respectively, and f s,min is the minimum switching frequency. once l p is determined, the rms current of the mosfet in normal operation are obtained as: rms peak max ds,max ds,max d ii 3 = (8) [d] determine the proper core and the minimum primary turns when designing the transformer, consider the maximum flux density swing in normal operation ( b max ). the maximum flux density swing in normal operation is related to the hysteresis loss in the core, while the maximum flux density in transient is related to the core saturation. from faraday?s law, the minimum number of turns for the transformer primary side is given by: pk 6 pds,max p,min max e li n10 ba = (9) where: l p is specified in equation 7; i ds,max pk is the peak drain current specified in equation 6; a e is the cross-sectional area of the core in mm 2 ; and b max is the maximum flux density swing in tesla. generally, it is possible to use b max =0.25~0.30 t. determine the number of turns for auxiliary winding the number of turns for auxiliary winding ( n a ) can be obtained by: dd d1 a od v+v n= v+v (10) where: v dd is the operating voltage for vdd pin; v d1 is the forward voltage drop of d 1 in figure 5; and v o and v d as determined in equation 2.
an-6300 application note ? 2009 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.2 ? 5/21/10 5 determine the startup circuitry when the power is turned on, the internal current (typically 1.2ma) charges the capacitor c 1 through a forward diode d 2 and a startup resistor r hv . during the startup sequence, the v ac from the ac terminal provides a startup current of about 1.2ma and charges the capacitor c 1 . r hv and d 2 series connections can be directly connected by v ac to the hv pin. as the vdd pin reaches the turn-on threshold voltage v dd-on , the fan6300/a/h activates and signals the mosfet. the hv startup circuit switches off and d 1 is turned on when the energy of the main transformer is delivered to secondary and auxiliary winding. 8 6 4 hv vdd gnd fan6300/a/h v ac d 2 r hv i hv d 1 c 1 t d-on v dd-on figure 5. startup circuit for power transfer the maximum power-on delay time is determined as: ma v c t on dd on d 2 . 1 1 ? ? = (11) where v dd-on is the fan6300/a/h turn-on threshold voltage and t d-on is the power-on delay time of the converter. if a shorter startup time is required, a two-step startup circuit, as shown in figure 6, is recommended. in this circuit, a smaller c 1 capacitor can be used to reduce the startup time. the energy supporting the fan6300/a/h after startup is mainly from a larger capacitor c 2 . 8 6 4 hv vdd gnd fan6300/a/h v ac d 2 r hv i hv d 1 c 1 t d-on v dd-on c 2 d 2 figure 6. two-step circuit providing power when the supply current is drawn from the transformer, it draws a leakage current of about 1 a for the hv pin. the maximum power dissipation of the r hv is: = hv 2 rhv-lc(typ.)hv pi r (12) where i hv-lc is the supply current drawn from the hv pin. hv r p = 1 a 2 x 100k ? ? w (13) the fan6300/a/h has a voltage detector on the vdd pin to ensure that the chip has enough power to drive the mosfet. figure 7 shows a hysteresis of the turn-on and turn-off threshold levels. i dd 4.5ma v dd 8v 10v 16v 80 a 10 a figure 7. uvlo specification the turn-on and turn-off threshold voltage are internally fixed at 16v and 10v. during startup, c 1 must be charged to 16v to enable the ic. th e capacitor continues to supply the v dd until the energy can be delivered from the auxiliary winding of the main transformer. the v dd must not drop below 10v during the startup sequence. if the secondary output short circuits or the feedback loop is open, the fb pin voltage rises rapidly toward the open- loop voltage, v fb-open . once the fb voltage remains above v fb-olp and lasts for t d-olp , the fan6300/a/h stops emitting output pulses. to further limit the input power under short-circuit or open-loop conditions, a special two- step uvlo mechanism has been built in to prolong this discharge time of the v dd capacitor. in figure 8, the two- step uvlo mechanism decreases the operating current and pulls the v dd voltage toward the v dd-off . this sinking current is disabled after the v dd drops below v dd-off . the v dd voltage is again charged towards v dd-on . with the addition of the two-step uvlo mechanism, the average input power during a short-circuit or open-loop condition is greatly reduced. when the gate pulses are emitted, the start-timer t starter with 30 s per cycle is enabled. the 30 s start timer is enabled during startup until the output voltage is established, when the feedback voltage (v fb ) is larger than 4.2v. figure 8. fan6300/a/h uvlo effect
an-6300 application note ? 2009 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.2 ? 5/21/10 6 detection pin circuitry figure 9 shows the det pin circuitry. the det pin is connected to an auxiliary winding by r det and r a . the voltage divider is used for the following purposes: ? detects the valley voltage of the switching waveform to achieve the valley voltage switching. this ensures qr operation, minimizes switching losses, and reduces emi. ? produces an offset to compensate the threshold voltage of the peak current limit to provide a constant power limit. the offset is generated in accordance with the input voltage with the pwm signal enabled. ? a voltage comparator and a 2.5v reference voltage provide an output ovp protection. the ratio of the divider determines what output voltage level to stop gate. 6 1 det vdd r det r a v aux + - figure 9. detection pin section first, determine the ratio of the voltage divider resisters. the ratio of the divider determines what output voltage level to stop gate. in figure 10, the sampling voltage v s is: =?? aa so sdeta nr vv nr+r <2.5v (14) where n a is the number of turns for the auxiliary winding and n s is the number of turns for the secondary winding. figure 11 shows the output voltage ovp detection block of using auxiliary winding to detect v o . in normal condition, v s is designed to be below 2.5v. the nominal voltage of v s is designed around 80% of the reference voltage 2.5v; thus, the recommended value for v s is 1.9v~2.1v. the output over-voltage protection works by the sampling voltage after the switching-off sequence. a 4 s blanking time ignores the leakage inductance ringing. if the det pin ovp is triggered, the power system enters latch mode until ac power is removed. figure 10. voltage sampled after 4s(1.5s for h version) blanking time after switch-off sequence 1 det s/h det ovp t off blanking (4s) v det latched 0.3v 2.5v 5v + - v o r a r det to vdd (1.5s) for h version figure 11. output voltage ovp detection block once the secondary-side switching current discharges to zero, a valley signal is generated on the det pin. it detects the valley voltage of the switching waveform to achieve the valley voltage switching. when the voltage of auxiliary winding v aux is negative (as defined in figure 9), the det pin voltage is clamped to 0.3v. r det is recommended as 150k to 220k to achieve valley voltage switching. after the platform voltage v s in figure 10 is determined, r a can be calculated by equation 14. figure 12 shows the internal valley detection block of fan6300/a/h. the internal timer (minimum t off time) prevents the system frequency from being too high. first valley switching is activated after minimum t off time 8 s(3s for h version) is counted. figure 13 shows a typical drain voltage waveform with first valley switching.
an-6300 application note ? 2009 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.2 ? 5/21/10 7 1 det t off- min (8s/38s) 5v valley detector v det 1st valley t off- min +9s v fb to sr f/f 0.3v 0.3v r a r det to vdd v aux + - v in (3s/13s) for h version t off-min +5s for h version figure 12. valley detection block figure 13. first valley switching the proprietary green-mode function provides off-time modulation to linearly decrease the switching frequency under light-load conditions. v fb , which is derived from the voltage feedback loop, is taken as the reference. in figure 14, once v fb is lower than 2.1v, the t off-min time increases linearly with lower v fb . the valley voltage detection signal does not start until the t off-min time finishes. therefore, the valley detect circuit is activated until the t off-min time finishes, which decreases the switching frequency and provides extended valley voltage switching. in very light load conditions, it might fail to detect the valley voltage after the t off-min expires. under this condition, an internal t time-out signal initiates a new cycle start after a 9 s(5s for h version) delay. figure 15 and figure 16 show the two different conditions . figure 14. v fb vs. t off-min curve figure 15. qr operation in extended valley voltage detection mode figure 16. internal t time_out initiates new cycle after failure to detect valley voltage (with 5s delay for FAN6300H) figure 17 shows the v fb vs. pwm frequency curve, where f s,min is the minimum switching frequency at the minimum input voltage and full load condition, f s,max is maximum switching frequency during first valley switching, and f s,g is the minimum frequency when a 9 s(5s for h version) timer is enabled. when output load is gradually lighter from maximum load, v fb becomes lower. once v fb is below 2.1v, the green-mode function is activated; thus t off time is extended linearly. the flyback converter is forced to enter discontinuous conduction mode (dcm); therefore, the switching frequency f s can be decreased once the mosfet drain voltage is switched at further extended valley voltage (2 nd , 3 rd , 4 th , 5 th ?valley, etc.). f s,g is larger than 20khz to prevent audio noise. once the converter enters deep dcm, v fb is lower than 1.2v. meanwhile, the
an-6300 application note ? 2009 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.2 ? 5/21/10 8 2ms timer t starter is enabled and f s is around 500hz to save power. switching frequency (hz) v fb 1.2v 2.1v f s,min f s,max 20k f s,g v fb,max 2k figure 17. v fb vs. switching frequency curve r det determines the extended valley switching capability. a typical value for r det is 150k-220k ? . a smaller value for r det enhances the extended valley switching capability, thus further extended valley voltage can be switched. in different applications, the falling time of the mosfet drain voltage (t f , in figure 4) may cause the valley switching voltage to be imprecise. adjust the r det value or add a capacitor c a connected from det pin to gnd may be helpful to the valley switching voltage. the recommended value for c a is below 22pf. r det also affects the h/l line constant power limit. to compensate this variation for wide ac input range, the det pin produces an offset voltage to compensate the threshold voltage of the peak current limit to provide a constant-power limit. the offset is generated in accordance with the input voltage when the pwm signal is enabled. this results in a lower current limit at high-line inputs than low-line inputs. at fixed-load condition, the cs limit is higher when the value of r det is higher. design the feedback control fan6300/a/h is designed for peak-current-mode control. current-to-voltage conversion is accomplished externally with a current-sense resistor r s . in normal operation, the fb level controls the peak inductor current i pk is: s fb pk r v i ? = 3 2 . 1 (15) where v fb is the voltage of fb pin. when v fb is less than 1.2v, the start-timer t starter , with 500 s per cycle, is enabled. figure 18 is a typical feedback circuit consisting mainly of a shunt regulator and opto-coupler. r 1 and r 2 from a voltage divider are for the output voltage regulation. r 3 and c 1 are adjusted for control-loop compensation. a small-value rc filter (e.g. r fb =10 ? , c fb = 10nf) placed on the fb pin to the gnd can further increase the stability. the maximum sourcing current of the fb pin is 1.2ma. the phototransistor must be capable of sinking this current to pull fb level down at no load. the value of the biasing resistor r b is determined as: ? odz b v-v-v k r 1.2ma (16) where: v d is the drop voltage of photodiode, approx. 1.2v; v z is the minimum operating voltage; 2.5v of the shunt regulator; and k is the current transfer rate ( ctr ) of the opto-coupler. for an output voltage v o = 5v, with ctr =100%, the maximum value of r b is 860 ? . fb v o r 1 r 2 r b r 3 c 1 r fb c fb figure 18. feedback circuit leading-edge blanking (leb) a voltage signal proportional to the mosfet current develops on the current-sense resistor r s . each time the mosfet is turned on, a spike induced by the diode reverse recovery and by the output capacitances of the modfet and diode, appears on the sensed signal. a leading-edge blanking time of about 300ns has been introduced to avoid premature termination of mosfet by the spike. therefore, only a small-value rc filter (e.g. 100 ? +470pf) is required between the sense pin and r s . a non-inductive resistor for the r s is recommended. figure 19. turn-on spike
an-6300 application note ? 2009 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.2 ? 5/21/10 9 output driver / soft driving the output stage is a fast totem-pole driver that can drive a mosfet gate directly. it is also equipped with a voltage clamping zener diode to protect the mosfet from damage caused by undesirable over-drive voltage. the output voltage is clamped at 18v. an internal pull- down resistor is used to avoid a floating state of the gate before startup. by integrating circuits to control the slew rate of switch-on rise time, the external resistor r g may not be necessary to reduce switching noise, improving emi performance. figure 20. gate drive transformer structure leakage inductance effect figure 21 shows the practical waveform on the mosfet drain terminal. when the mosfet turns off, a voltage spike ( v spike ) is produced on the drain terminal owing to the transformer leakage inductance. the leak inductance is not easily calculable, but it can be minimized through the secondary windings between halves of the primary. meanwhile, the voltage waveform on the auxiliary winding is similar to that on the mosfet drain terminal. these spike voltages contribute extra energy to the v dd capacitor, which ruins the relationship between v dd voltage and the output voltage. figure 21. mosfet drain voltage waveform two kinds of commonly used transformer structure are introduced as follows: structure type a: structure type a is sandwiching winding method. the power supply is mostly used sandwiching the secondary windings in between halves of the primary, especially when the output power is large. the auxiliary winding is at the top layer by increasing thickness between the primary winding. this course of action can reduce the leakage inductance and increase the coupling between the primary and the secondary winding. it can also improve the conversion efficiency and reduce the voltage spike on the mosfet owing to transformer leakage inductance. however, it reflects the voltage spike on auxiliary winding easily and causes a large voltage deviation on v dd in light-load and heavy-load conditions. structure type b: another kind of transformer structure is stacked winding method, usually used in the switching power supplies with smaller output power. this method produces worse coupling between primary and secondary winding than structure a; therefore, the voltage spike on the mosfet is higher and the conversion efficiency is lower. figure 22 shows the modified structure of type a for sandwiching winding. the auxiliary and secondary windings are between halves of the primary windings. with this method, smaller voltage deviation on v dd in light load and heavy load can be achieved. meanwhile, the output voltage ovp level is more precise. therefore, the recommended transformer stru cture for the adaptor is shown as figure 22. winding primary winding secondary winding (insulated) primary winding auxiliary figure 22. sandwiching winding structure
an-6300 application note ? 2009 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.2 ? 5/21/10 10 lab note before modifying or soldering/desoldering the power supply, to discharge the primary capacitors through the external bleeding resistor. otherwise, the pwm ic may be destroyed by external high-voltage during the process. this device is sensitive to electrostatic discharge (esd). to improve the production yield, the production line should be esd protected as required by ansi esd s1.1, esd s1.4, esd s7.1, esd stm 12.1, and eos/esd s6.1 standards. printed circuit board layout current/voltage/switching frequency make printed circuit board layout and design a very important issue. good pcb layout minimizes excessive emi and prevents the power supply from being disrupted during surge/esd tests. guidelines: ? to get better emi performance and reduce line frequency ripples, the output of the bridge rectifier should be connected to capacitor c bulk first, then to the switching circuits. ? the high-frequency current loop is found in c bulk ? transformer ? mosfet ? r s ? c bulk . the area enclosed by this current loop should be as small as possible. keep the traces (especially 4 1 ) short, direct, and wide. high-voltage drain traces related the mosfet and rcd snubber should be kept far way from control circuits to prevent unnecessary interference. if a heatsink is used for the mosfet, ground the heatsink. ? as indicated by 3 , the control circuits? ground should be connected first, then to other circuitry. ? as indicated by 2 , the area enclosed by the transformer auxiliary winding, d 1 , and c 1 should also be kept small. place c1 close to the fan6300/a/h for good decoupling. two suggestions with different pros and cons for ground connections are recommended: ? gnd 3 2 4 1 : possible method for circumventing the sense signals common impedance interference. ? gnd 3 2 1 4 : potentially better for esd testing where a ground is not available for the power supply. the charges for esd discharge path go from secondary through the transformer stray capacitance to the gnd 2 first. then, the charges go from gnd 2 to gnd 1 and back to the mains. control circuits should not be placed on the discharge path. point discharge for common choke can decrease high-frequency impedance and help increase esd immunity. ? should a y-cap between primary and secondary be required, the y-cap should be connected to the positive terminal of the c bulk (v dc ) . if this y-cap is connected to the primary gnd, it should be connected to the negative terminal of the c bulk (gnd 1 ) directly. point discharge of the y-cap also helps with esd. however, according to safety requirements, the creepage between the two pointed ends should be at least 5mm. figure 23. layout considerations
an-6300 application note ? 2009 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.2 ? 5/21/10 11 design example this section shows a design example of 90w (19v/4.74a) adaptor using qr pwm controller fan6300/a/h and boundary conduction mode pfc controller fan6961. the pfc output voltage is 260v at low ac input voltage, 400v at high ac input voltage. from the specification, all critical components are treated and final measurement results are given. table 1. system specification input input voltage range 90~264v ac line frequency range 47~63hz output output voltage ( v o ) 19v output power ( p o ) 90w minimum switching frequency ( f s,min ) 50khz based on the design guideline, the critical parameters are calculated and summarized as shown in table 2. table 2. critical system parameters d max 0.327 n 6.8 i ds,max pk 2.429a l p 700h v in,min 260v v in,max 400v v ds,max 533.28v v d 0.6v t f 0.6 s 0.87 n p 34t n s 5t n aux 4t 6 4 8 7 2 1 5 3 hv fb det gate cs gnd vdd nc pfc stage c 1 + - v o emi filter ac input l n r 1 c 6 c 5 c 4 c 3 c 12 c 2 c 11 c 7 c 9 r 2 r 3 r 4 r 5 r 6 r 7 r 8 r 11 r 12 r 14 r 13 r 10 l 1 d 6 d 2 d 5 d 3 d 4 d 1 q 1 c 13 ic 1 fan6300/a/h ic 2 ic 3 bd 1 c 8 r 9 c 10 figure 24. complete circuit diagram
an-6300 application note ? 2009 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.2 ? 5/21/10 12 table 3. bill of materials part value note part value note resistor mosfet r 1 100k 1/4w q 1 fdp15n65 15a/650v r 2 68k 2w inductor r 3 0 1/4w l 1 3h r 4 180k 1/4w ic r 5 27k 1/4w ic 1 fan6300/a/h r 6 10 1/4w ic 2 pc817 r 7 100 1/4w ic 3 tl431 r 8 0.2 2w diode r 9 47k 1/4w d 1 0.5a/600v r 10 33 1/2w d 2 byv95c r 11 220 1/4w d 3 fr103 r 12 68k 1/4w d 4 1n4148 r 13 10k 1/4w d 5 20a/100v schottky diode r 14 1.6k 1/4w d 6 20a/100v schottky diode bd 1 4a/600v bridge diode capacitor c 1 68f 450v c 12 22nf c 2 3.3nf 630v c 13 222p/250v y-capacitor c 3 47f 50v c 4 10f 50v c 5 470pf c 6 47nf c 7 1000f 25v c 8 470f 25v c 9 470f 25v c 10 470f 25v c 11 1nf 1kv
an-6300 application note ? 2009 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.2 ? 5/21/10 13 related datasheets fan6300 ? highly integrated quasi-resonant current pwm controller disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function, or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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